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KevL
United Kingdom
78 Posts |
 Posted - 26 Aug 2010 : 12:29:33
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I get the impression that EPC was originally designed to be very flexible. This has pros and cons. It allows the thorny issue of what is best practice to be ignored and it also allows anyone to configure it however they want - in principle. It would certainly benefit from a new approach which would be based around a “best practice” approach to Schematic/PCB creation philosophy and allowing the package to be setup to support this. I guess it should still allow the user to do anything they want - however non preferred - but out of the box it should work in the best practice manner.
I also get the feeling that since EPC has been evolving with time then a trick was missed in thinking through and describing in detail how one should set up all the libraries in the first place. No attempt was made to force a best practice way of working. Thus there are many different ways of setting up schematic symbols (display of value fields, use of symbols with or without hidden connectivity, line styles) and for pcb footprints (use of layers, styles, drawing standards).
Because of this fundamental flexibility it is unlikely any two users have the same configurations. This is a shame and it complicates fixing the situation no end.
With regard to footprints then last time I looked at EPC’s standard libraries then it seemed they have a very simple layer structure. Copper layer(s) and a silkscreen layer. Seems reasonable but not very useful for a fully integrated CAD setup which will almost inevitably involve a the need to exchange data with 3d mechanical CAD type setups.
EPC has the ability to display value fields in schematics - which is useful (essential) and in PCBs - which is neither essential nor useful. Similarly Pin names and numbers can be displayed in schematics (essential) and these can usefully be switched on and off to suit individual component requirements. Confusingly PCB items can also have a pin name and pin number made visible. But pin number field can display pin number, pin name and net name. The pin name field can also display pin number, pin name and net name. How is one supposed to use these settings???? Flexible - yes, confusing - yes, useful - not sure.
Again taking a quick look at schematic symbol libraries supplied by EPC (some time ago, they may be better now) then the fields were setup so that next to resistor then one would see something like
R56
1k
Where 1k is the value
But given that the schematic is the primary piece of documentation an electronic engineer produces one has to ask - is this adequate?
I would argue that every component on a schematic should be completely identifiable from the schematic. How else can the design be reviewed? Surely something like
R56
1k
0603
Would be the absolute minimum that would be acceptable providing the schematic had a note saying something like all resistors shall be 1% unless otherwise stated. The fact that the 0603 package is stated allows me to know the power rating. I.e. I can know from the schematic that the part is fit for purpose and sign off the review documentation with some confidence. I can do this easily without referring to a BOM etc.
So surely the example library items should be configured for the best practice approach….
Of course it can be argued that one can add as many values to a symbol as one wishes - even at schematic level. Such people must really like typing. If you define them at library level then you only type all the stuff in once. We have set our libraries up so that e.g. resistors have their own library and in it there are around a dozen ranges of parts. The way we do this is by having 12 components with names such as
R 0402 1R-1M E12
R CF 1W 10R-1K 5% E6
Etc
So I have a range of 0402 resistors they are 1% (by default so not stated). Values are from 1ohm to 1meg in E12 (12values per decade).
When the symbol is placed on the schematic I get THE resistor symbol with the following values
R56
1R-1M E12
0402
I then edit the top field by being guided by the initial text string so I end up with
R56
10k
0402
Same idea for caps etc but in the case of caps you have to deal with more component ranges as NP0 gives up at 1n (say) X7R at 100n (say) and so you end up with far more components in the capacitors library than in the resistor library. The key thing is that we only ever have to edit the top value to distinguish it from others in the same component and also the footprint for all the values possible in a single component is always the same.
So for Caps we might initially place
C 1206 1n-22n E6 200V NPO
Symbol shows
C56
1n-22n E6/200V
NP0
1206
Which gets edited to
C56
22n/200V
NPO
1206
Etc.
Many components are unique and in this case there is no editing to do at all. Place it and fine-tune value placement and move on.
We can then generate a BOM report from the schematic as a CSV. We take Reference designator, component name and a couple of value fields and run this through a trivial piece of VB which checks that the parts are valid (I.e. exist in an external database) and generates fully costed BOMs with supplier parts numbers etc ready to be emailed to suppliers as needed. All with very little typing. So my use of value fields is to inform. I’m not trying to make the EPC libraries keep extensive data, that is kept elsewhere by tools more suited to the task.
So I will try to spell out how I would configure the libraries for what I would regard as “best practice”. I am very aware of the difficulty of trying to set this out. There is no 1 way of arranging things. But you have to start somewhere. Here is how we set our symbols up.
Symbols
1. All pins on a 100 mil grid. Nice tidy schematics all pins/wires on grid
2. All drawn with a standard line type. With 1 or a very few controlled line styles I can trivially customise print plot output (for best print clarity) with 1 setting in the schematic.
3. Maximum reuse of all symbols. Only 1 resistor symbol reused many times. One non-polar cap symbol, one polarised cap symbol etc.
4. Two pin devices R,C, L, D etc all have symbols 500mil high. This makes very tidy schematics.
5. ICs have inputs on left outputs on right if appropriate.
6. Logic gate symbols are all the same size and the shape of the symbol shows function for AND/OR etc (I never got the hang of IEEE symbols)
7. Power pins are drawn as a separate gate symbol so that they don’t get in the way of the logic. They with de-couplers are shown at the bottom of schematic sheets for best clarity.
8. Op-amps use standard triangle symbol but have separate power wires (drawn as a separate gate symbol with two vertical lines) and are positioned around the triangle. This then allows the triangle to be flipped to change location of +/- inputs for best clarity.
9. Connectors drawn as boxes (usually) but with the box giving a symbolic view of the connector when looking into it. So a D-type is shown as a box with a d-type representation inside.
10. Value fields, 2 or 3 fields are shown. Enough info to completely identify parts. For Rs this is value and (tol. if not 1%), e.g. 10K 0.1% and package e.g. 0805
For C this is 10n/50V, X7R and 1206. For mosfet part name BS123 and package SOT-23. For electrolytic caps 100uF/25V and manufacturer and series name e.g. Panasonic and YXF.
11. All schematic symbol fonts, net label fonts 10pt Arial.
12. Pins on symbols were pin number is shown are 200long, where no number is shown they are made 100mil long.
13. All ref origins are standard positions.
14. Even SPICE symbols use the same symbols so that I can easily change a standard schematic to call spice symbols for simulation without redrawing. This is because I haven’t got around to integrating SPICE and PCB components so that I can simulate from ordinary schematics. Just a matter of playing with value fields but haven’t had time.
Anyway as long as the symbols are consistently drawn and schematics are tidy and easy to read I don’t suppose it matters.
What is does show as that only a very few primitive styles are needed and used. 1 line-type, 1 font, 1 pin style. Occasionally a dashed line for relays etc and a thicker line in some switch a relay symbols.
I would really like it if I could nail down the symbol editor to only use the preferred styles - or at least require some effort to use new styles.
Footprints.
These are much more complex than schematic symbols as the concept of layers is involved.
This then begs the question how should layers be configured for best applicability to best practice setups. I cant say I have the absolute answer to this - there probably isn’t one - but taking a look at a few good data sources e.g. Mentor Graphics IPC SM footprint tools suggests that the below list might be a start.
Silkscreen
Mechanical Drawing Layer
Footprint Courtyard
Solder Mask
Paste Mask
Copper Layers(s)
Silkscreen as we know is just some paint that get applied to the top of the PCB to ease component insertion and identification. As technology shrinks dimensions it is becoming less useful. Text sizes on tight SM PCBs often need to be smaller than can be clearly printed - or else they cannot be fitted in. Also paint must miss pads and must be say 4mil or so away from pads to allow screen miss-alignment/bleed effects. Warning…. Last time I looked the EPC libraries did not seem to adhere to this rule. Paint on pads is bad news for defect free soldering. So silkscreen often bears no resemblance to actual mechanical outline of the part. Silkscreen is thus NOT a useful basis of component geometry for export to 3d CAD and on tight layouts may not even be a very good guide to component placement (some text may be missing as it wouldn’t fit)
The mechanical drawing layer is used to allow assembly and mechanical information to be generated. The mechanical outline of the components is drawn as an accurate 2d representation of the component. We draw these in a 1mil thick line. We show the body of the component (often a simple rectangle), the lead extent and the lead landing area of the lead on SM packages. We also include orientation info (notches in packages, + signs, bars in diodes etc) and a reference designator (R symbol) which is set to be centred in the component outline. We don’t have to worry about this being visible on the populated board like we do for silkscreen so this gives us a proper assembly drawing with very little effort. We include landing area of leads in the mechanical drawing as it allows us to sanity check the placement of pads. This layer info can then be exported to 3d CAD by DXF or IDF and we get a good representation of the finished PCB to allow casework design, eliminate clashes, design wiring looms etc. We try to keep the outline simple so often when complicated connector shapes are imported from dxf files into the footprints we spend time deleting lots of over-fussy outline info.
Footprint Courtyard is a simple box around many SM parts and is defined in the IPC specs. I think the idea is that it gives the assembly machines space to get the on-sertion head in. Clashes between footprint courtyards on PCBs often need investigation/correction.
Paste mask and Solder resist need to have defined layers in the library. This is because only standard (simple) pad shapes get the mask shapes defined at PCB level. There are some components which need strange pad shapes, made by having a simple pad surrounded by a drawn, filled shape. Such shapes need to have the paste and solder mask shapes drawn also (with suitable expansions/contractions taken into account). Also some packages need the paste mask to be made from an array of smaller squares on large central pads.
Copper layers are obvious. Typically pads will be either SM on the top or through hole. Occasionally there is the need to have pads on the bottom layer for the odd part (e.g. some RF packages) that get fitted through routed holes in the PCB and are soldered to bottom layer pads and the package protrudes through the pcb and has parts above the top face. It may thus have 2 mechanical drawings, for top and bottom outline. Also such parts need to have some routing defined. We do this by having a line width of 1.6mm to suit our pcb manufacturers preferred router diameter. We draw the router path on a layer labelled Routing layer - strangely - and this layer is also used to draw the path of the router cutter which cuts the pcb board profile on finished board. Similarly PCB edge connectors e.g. PCI PCB tails need double sided SM pads and have the profile defined in the routing layer. This complication means we need to have the following layers defined - but at least this is comprehensive - because the way the libraries are currently managed you wouldn’t want to have to change your mind half way through setting up your libraries - been there, done that.
Top Silkscreen
Top Mechanical Drawing
Top Footprint Courtyard
Top Solder Mask
Top Paste Mask
Top Copper
Bottom Copper
Bottom Paste Mask
Bottom Solder Mask
Bottom Footprint Courtyard
Bottom Mechanical Drawing
Bottom Silkscreen
Routing Layer
I think the above should be adequate for most applications. The only other layers that I could think of adding would be a couple of internal copper layers. I think I have used such things in the past when thermal ladders are used on SM heat sinks. In these cases you want the copper in the internal layers to help transfer heat through the board but there is a problem with this thinking. If you put in internal layers then you need to define all the layers you might ever need. Maybe best to treat such heat sinks as structures you simply have to tailor to the particular pcb arrangement. They are quite uncommon features anyway and will doubtless require extreme customisation depending on application.
For mechanical drawings we use 1mil line
For silkscreen we use 8mil line
It actually doesn’t matter as long as there is consistency in style naming. If styles worked as they should then one day when silkscreen printing is more precise then one ought to be able to redefine silkscreen outline style as 5mil line say.
With regard to technology files we only use 4
Schematic Tech
Schematic Lib Tech
PCB Tech
PCB Lib Tech
The PCB tech file has layer definitions for a 6 layer PCB - which is as many layers as I ever use. 2 layer PCBs are made using the 6layer standard tech file and we just delete un-needed layers. This is not much of an issue as it takes only a few seconds once per layout. I probably could setup multiple PCB tech files but like to keep it simple.
So given the above - which is a reasonable starting point - though I’m sure others have better ways of arranging things. If we decide that we really do want consistent layer and line definitions applied to our libraries then how can this be achieved given that we are were we are. (And I’m included here also). We strove for consistency but didn’t manage to get there. We often adjust the silkscreen font height for different PCB processes. We do this at PCB level as it is a single settings and should apply to all items.
We often observe that while 95% of silkscreen fonts change size as required - some don’t because they have been given the wrong style name. More editing footprints in the libraries follows. I suppose we’ll get there in the end but did it really have to be this difficult?
I guess the point I’m trying to make is that EPC should guide us to use a method of arranging things which would guarantee a successful outcome. Standardisation might even allow users to exchange library items etc with only minor changes needed to suit local drafting standards. I bet if users tried swapping library items at the moment the almost complete redrawing would be needed. If our layer usage was “standardised” many of the features in EPC could be made much more useful. E.g. The 3d visualisation tool would do a better job if it simple extruded the mechanical layer to the height specified in the height field rather than attempting to use the silkscreen layer.
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Library Configuration for Best Practice
