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KevL
United Kingdom
78 Posts |
 Posted - 26 Aug 2010 : 12:26:54
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Optimal Library integration needs to consider how EPC is used I.e. the PCB design process. This allows its functions to be streamlined, needed functionality made accessible and unneeded functionality made less prominent.
I am firmly of the opinion that the most important thing about a PCB package installation is the quality of the libraries. The ability of the package to join tracks of different widths to pads, in accordance with the netlist is simply assumed. Lib elements are the building blocks - if they are correct then the PCB might be. If they are not then abandon hope. I also believe that fixing incorrect lib items at PCB level is a very poor way to work (that’s putting it mildly). You might remember to bodge the incorrect item next time the PCB / schematic is reworked but will another engineer / technician remember to do it in say 6months time when he is just tidying up a wire strap on a board? Best fix any symbol/footprint issues in the lib once and absolutely avoid doing so at PCB level. I’m no fan of pad exceptions for this very reason. There shouldn’t be any! I think they are a bodge to be applied as a last resort. If you leave such things lying around on a PCB will anyone notice if they accidentally clear them during some process? If a footprint variant is needed to overcome some geometry issue then it is a simple matter to create a suitably name footprint variant in the library and apply it as needed.
To my mind the package should provide the following capability.
1. Allow clear accurate aesthetically pleasing circuit diagrams to be easily generated. These should clearly and unambiguously define all connectivity (there must be no hidden connectivity). I can’t see hidden connectivity when I review schematics so I insist that none exists. The circuit diagram should allow all components to be unambiguously identified so that an engineer placing a symbol on a schematic should have complete certainty about what is going to turn up on the PCB and the finished product.
Schematics symbols should include enough displayed information to make this determination possible without recourse to BOMs or other external documents. Complex electronic design is hard enough without the added complication of wondering what characteristics simple passives might actually possess. I might need to refer to datasheets to ensure a design is valid but having to cross refer to a printed BOM to tell me what the parts actually are is an easily avoided complication.
2. The PCB package should accept netlist and other info from the schematic and should allow the PCB to be designed. The PCB should not have the power to change the netlist. If the netlist is wrong it should be changed in the schematic and changes sent forward.
3. The schematic should be supplied with DRC tools enough to warn of likely problems (e.g. connectivity provided by hidden named nets, floating digital inputs, floating power pins). The DRC report should be such that only valid errors are reported. There is no point having a DRC report in which a few real errors are obscured by lots of un-real errors. The PCB package should include enough tools to allow netlist connectivity to be checked against the schematic. It should also allow clearances and important manufacturing rules to be verified.
On the whole I think EPC meets the above requirements though it does have some foibles. E.g.
It seems to allow nets to be added to PCBs,
generates lots of bogus errors for example when a bus is carried over multiple sheets etc.
Incorrect connectivity can be added at PCB stage when unconnected pads are accidentally joined by tracks. I’m fairly sure such errors are not detected by the DRC.
Why would anyone want to add nets at PCB level?. How could such additions be approved / signed off?. Why would anyone want a PCB that had connectivity that was not as described/dictated by the schematic? Many years ago it was a fairly common practice to hide the 5V supply to logic parts to aid clarity. Modern digital design make this approach dangerous. I can’t remember the last time I design a digital circuit with only a single digital supply a mixture of 5V, 3V3 and lower voltages are now more common. Also with the need to conserve power whenever possible there may even be more than 1 supply with a voltage of say 5V. Hidden connectivity is thus dangerous. It easily has the ability to be unintended connectivity.
On the whole I think EPC is a very capable package for drawing schematics and PCBs and it keeps being improved. There are a few fairly minor and easily fixed problems. It would be a very expensive or simple piece of software (and EPC is neither) if it was utterly without possibility of improvement.
In my view what is needed for the above to be improved are attention to automating things which are currently time consuming manual operations e.g. provide a means to automatically renumber components by clicking on items in sequence - like the pin renumbering algorithm employed for schematic and pcb symbol/footprint pins/pads. I.e. click on first resistor and it becomes R1, next resistor R2 etc. If I then add an R4 then renumber the old R4 to R5, old R5 to R6 etc. The automated renumbering of schematic symbols is currently un-usable. Might better be called random renumber. Then make forward annotation to PCB work properly - renumber the footprints, don’t rip up the tracks and move footprints about. If you lay out a PCB with R1 and R2 and then swap the reference designators in schematic and forward annotate it will rip up the tracks and move 1 component to the bin….. Hours wasted. Handle busses properly. Give them a name and allow similarly named buses to be added to a second schematic sheet. Named busses contain a set of signals so the package can tell that pins enter bus and leave it - even if on a different sheet. Thus avoid the bogus DRC “error” - signal only connected to bus once - which is bound to hide real problems occasionally. Make the schematic technology file include nets for all schematics in a project, not sheet by sheet. I.e. a few tweaks to remove repetitive tasks and increase productivity = reduce cost of ownership.
K
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davep
United Kingdom
101 Posts |
Posted - 26 Aug 2010 : 12:47:10
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Adding everything to a schematic symbol can really clutter up a drawing.
Take a capacitor: Capacitance, Voltage, ESR, ESL, Ripple rating etc.
Sometimes it is not known what values will be used.
1) New design - we know the circuit, want the prototype board on order but haven't calculated the actual values.
2) Several variants of the circuit each with it's own list.
I place just circuit references and use a separate BOM creation routine which matches the empty symbols in an Easy-PC file with attributes I keep in an Access database. |
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KevL
United Kingdom
78 Posts |
Posted - 26 Aug 2010 : 14:00:38
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I guess thats just a different equally valid way of working.
We work by having designed the circuit before we go to layout. We aim to draw one schematic once and have 1 layout. We try not to do rework. Sometimes (though not always) manage it too.
Not necessary to have all the datasheet on the schematic just enough info to tell what the part is. When there are a set of preferred parts (approved for cost, reliability, availability from preferred suppliers etc) then two or 3 fields really is enough info.
I and other engineers can tell whether an electroltic is low impedance, standard etc just from series code.)
Kev |
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Library Usage Philosophy