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 Gerber plot of Top Silk comes out solid

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T O P I C    R E V I E W
ricobasso Posted - 10 Sep 2024 : 11:21:58
Easy-PC Version 18.0.8
Never had this problem before; all the other layers look fine on a gerber viewer but the top silk is solid except for the pads and vias, which have a clearance around them, but I can't see any writing at all. No component outlines or ids. Any ideas as to what has gone wrong?
I uploaded anyway to the JLCPCB site, to have a look, and the whole board looks white!

2   L A T E S T    R E P L I E S    (Newest First)
ricobasso Posted - 10 Sep 2024 : 13:15:33
No, it is set to non-electrical.

I ran a Gerber plot of the top silk separately with the board outline set to "N" and that fixed it.

I must admit I still find the Output>Plotting and Printing>Gerber form settings a challenge.
edrees Posted - 10 Sep 2024 : 11:34:49
Sounds as if the Top silk screen is an electrical (flood pour) layer.
Check your layer types in the Design Tech file. Silk screen should be set to Non-Electrical.