Easy-PC Version 18.0.8 Never had this problem before; all the other layers look fine on a gerber viewer but the top silk is solid except for the pads and vias, which have a clearance around them, but I can't see any writing at all. No component outlines or ids. Any ideas as to what has gone wrong? I uploaded anyway to the JLCPCB site, to have a look, and the whole board looks white!
Sounds as if the Top silk screen is an electrical (flood pour) layer. Check your layer types in the Design Tech file. Silk screen should be set to Non-Electrical.
Gerber plot of Top Silk comes out solid
Posted - 10 Sep 2024 : 11:21:58
