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Screensize: 640 x 480 800 x 600 1024 x 768 1280 x 1024 UserName: Password: Format Mode: Basic  Help  Prompt  Format: Font Andale Mono Arial Arial Black Book Antiqua Century Gothic Comic Sans MS Courier New Georgia Impact Lucida Console Script MT Bold Stencil Tahoma Times New Roman Trebuchet MS Verdana   Size 1 2 3 4 5 6   Color Black Red Yellow Pink Green Orange Purple Blue Beige Brown Teal Navy Maroon LimeGreen Message: * HTML is OFF * Forum Code is ON Smilies [quote][i]Originally posted by jmathew[/i] [br]Hi, Any provision to display whole net in a symbol or in a gate in schematic, instead of pick up each net & display. It will be very usefull when doing with high count FPGA [/quote]   Check here to include your profile signature. Check here to subscribe to this topic.