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jmathew

India
17 Posts
Posted - 02 May 2010 :  19:43:35  Show Profile  Reply with Quote
Hi,

Any provision to display whole net in a symbol or in a gate in

schematic, instead of pick up each net & display. It will be very

usefull when doing with high count FPGA

Peter Johnson

United Kingdom
498 Posts
Posted - 11 May 2010 :  10:28:10  Show Profile  Visit Peter Johnson's Homepage  Reply with Quote
Not at present. I've added it to the wish list.
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