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Mike Warren
Australia
124 Posts |
 Posted - 21 Jun 2013 : 01:06:13
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Is there a way of putting thermal vias under chips without generating a bunch of DRC errors?
I need to use a TPA3110, under which I need to place a large number of thermal vias. These also need to have paste on them so I can't use standard through-hole pads.
Any ideas?
How do other people handle this increasingly common requirement in EPC? |
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wprov
United Kingdom
15 Posts |
Posted - 28 Jun 2013 : 10:29:19
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Hi Mike,
I'm supprised you have not had a response on this subject though being a pcb subject would be more suited in the PCB section where has been talked about already.
Looking at the TI data sheet I would suggest using the component approach thus a bulk of "hacks" will follow moving the component !. Thus :
a) Create all the part lead pads 1-28 (top copper) no hole not plated.
b) Add larger centre rectangle pad (pad 29) for improved thermal distribution (top layer) keep hole set for drill diameter for thermal holes & plated.
c) Add the centre rectangle pad (pad 30) for the power pad (top layer) no hole not plated.
d) Add the 19 round pads (pads 31-51) (plated with small anular ring i.e. almost same size as drill hole).
e) In the pad properties change the pad names for unique names for (b), (c) & (d) like FXxxxxx !.
f) For (b) add exceptions on resist & paste layers i.e. change to 0 width & 0 length.
g) For (c) add exceptions on copper layers i.e. change to 0 width & 0 length.
h) For (d) add exceptions on copper, resist & paste layers i.e. change to 0 diameter.
For SCH part you could have 28 + 1 pins then when make component have normal 28 pin signals with a single pin for thermal pad or have 21 pins !.
When add to a pcb you must then "add net" to all holes 31-51 to same net as thermal pad 29. Add copper pour on desired layers surounding the holes (usualy same shape as larger thermal pad) with no thermal relieve & no remove small fill thus all pads fully linked to copper pour. When pour main copper with same net name as thermal pad net with normal options other pads will have thermal reliefs.
You need to make sure you have the resist & paste layer enabled in the pcb project. Providing you have applied exceptions correctly then each special effect pads will pass error checks by effectively describing virtual pads on each layer (top & bottom (copper, resist & paste)) as well as inner layers !.
You can then add component to a new pcb then output gerbers and check that the part has been set up correctly i.e. 1-28 + 29 on top copper, 1-28 + 30 on top resist & 1-28 + 30 on top paste (resist & paste same size else add another pad to have seperate resist & paste sizes). If exception applied to both top & bottom then when flipped the special pads will have same effect.
Drill file plated should show holes in the thermal pad area.
At least all this works in V11 as done for other TI parts that also has special requirements etc. If still in doubt then could make up part & send via peter or david forum permitting.
Sorry for this slow response as not on the internet much these day's.
wprov. |
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Mike Warren
Australia
124 Posts |
Posted - 28 Jun 2013 : 12:36:15
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Thanks for the detailed reply. I've had to put that job aside to get some programming done, but should be back to it on Tuesday or Wednesday.
I'll give it a go.
http://mike-warren.net |
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Mike Warren
Australia
124 Posts |
Posted - 28 Jun 2013 : 12:45:46
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What you said about needing to add the extra pads to the ground net manually is something that constantly bothers me with a lot of components that have multiple pins connected internally. For example, it would be nice to have a single component fro 3 terminal linear regulators, but a lot of the SM packages actually have 4 pins that must be connected.
It's necessary to either have separate schematic symbols for the different packages or manually add the extra pin to the appropriate net.
http://mike-warren.net |
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edrees
United Kingdom
779 Posts |
Posted - 28 Jun 2013 : 14:13:07
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Hi, Mike,
I think this is what you might be looking for,-
You can add numerous pcb pins to one schematic pin.
Example for my LM317 SOIC8, voltage regulator,-
YBLOCK,, Vin,, 1,, 1,, 1,,
Vo,, 2,, 2,3,6,7,, 2,3,6,7
Adj,, 3,, 4,, 4,,
(double comma used to indicate columns in component editor).
Hope this helps.
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Mike Warren
Australia
124 Posts |
Posted - 28 Jun 2013 : 14:21:55
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Thanks Ed,
That's exactly what I was looking for. How long has this ability been in EPC?
http://mike-warren.net |
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edrees
United Kingdom
779 Posts |
Posted - 28 Jun 2013 : 14:50:43
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I believe it's been around for quite some time Mike.
Occasionally, we all need pointing to some of theses little gems that exist in EPC without our knowing, that other Users just take for granted!
Hope you're comfortably numb now, -keep up with the PF! |
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John Baraclough
United Kingdom
129 Posts |
Posted - 28 Jun 2013 : 16:54:22
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If it helps, here's a screen dump from the component editor for a TDA1905 which has multiple pins connected to one schematic pin.
http://www.mydesk.myzen.co.uk/_Useful/EasyPcCompEd.jpg
This feature has been around since at least version 10 or 12 as I was using it before I retired eight years ago!
Birthdays are good for you: the more you have, the longer you live. |
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Iain Wilkie
United Kingdom
1015 Posts |
Posted - 28 Jun 2013 : 18:02:08
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On chips that have a thermal pad under the chip, just add this pad as an extra sm pad. On the layout simply add vias on top of this pad but remember to add these to the same net name as the thermal pad. The main pad will dictate the paste. No DRC errors.
Simples
Iain |
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Mike Warren
Australia
124 Posts |
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Mike Warren
Australia
124 Posts |
Posted - 29 Jun 2013 : 00:16:37
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quote:
Originally posted by edrees
Occasionally, we all need pointing to some of theses little gems that exist in EPC without our knowing, that other Users just take for granted!
I wonder how many other features I'd use that I'm not aware of there are. I guess since I'm not a heavy user (I can go six months or more without starting EPC) I tend to miss these things. I got EPC at V7 in March 2004 and only upgraded at 9, 10, 13, and 16, and only then because a feature of the new version was something I could immediately use.
I should go and download all the release notes (if they're still available) of each upgrade.
quote:
Hope you're comfortably numb now, -keep up with the PF!
 That was a fun, if time consuming project.
http://mike-warren.net |
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Mike Warren
Australia
124 Posts |
Posted - 29 Jun 2013 : 00:18:01
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quote:
Originally posted by John Baraclough
If it helps, here's a screen dump from the component editor for a TDA1905 which has multiple pins connected to one schematic pin.
http://www.mydesk.myzen.co.uk/_Useful/EasyPcCompEd.jpg
This feature has been around since at least version 10 or 12 as I was using it before I retired eight years ago!
Thanks John.
http://mike-warren.net |
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Iain Wilkie
United Kingdom
1015 Posts |
Posted - 01 Jul 2013 : 20:26:37
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quote:
Originally posted by Mike Warren
Iain, won't that generate a pad-via spacing error?
http://mike-warren.net
No because the pads and the vias are connected to the same net, so no DRC error. I use this all the time.
Iain
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Iain Wilkie
United Kingdom
1015 Posts |
Posted - 01 Jul 2013 : 20:32:34
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quote:
Originally posted by Mike Warren
quote:
Originally posted by edrees
Occasionally, we all need pointing to some of theses little gems that exist in EPC without our knowing, that other Users just take for granted!
I wonder how many other features I'd use that I'm not aware of there are. I guess since I'm not a heavy user (I can go six months or more without starting EPC) I tend to miss these things. I got EPC at V7 in March 2004 and only upgraded at 9, 10, 13, and 16, and only then because a feature of the new version was something I could immediately use.
I should go and download all the release notes (if they're still available) of each upgrade.
quote:
Hope you're comfortably numb now, -keep up with the PF!
That was a fun, if time consuming project.
http://mike-warren.net
There are lots of these little gems, my favourite is the "Net Match" in the spacings dialogue. This is a very powerful feature that allows selective variations in the Drc checking where for instance you wish a different spacing on different layers.
Iain |
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Topic |
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Thermal Vias Under Chips