|
shadders
United Kingdom
224 Posts |
 Posted - 31 Aug 2010 : 12:30:14
|
Hi,
Just spoken to a PCB manufacturer, and they have stated that the minimum hole that they can provide is 0.3mm. The next specification from them is that they need 0.5mm between the hole and copper clearance on an inner layer.
On the Technology File - Spacings there is the usual Via to Shape spacing.
This does not take into account Shape to Hole spacing on inner layers.
So to obtain the Shape to Hole spacing i have to set the Shape to Via spacing to 0.5mm, which provides a larger than 0.5mm spacing to a hole since the Via pad is greater than the hole.
I could calculate that all Vias have perhaps 0.2mm extra copper around the hole, and set the space for Via to Shape to be 0.3mm.
Is this a reasonable request - for Shape to Hole spacing for inner layers ?.
Thanks and regards,
Richard. |
|
Technology Spacings - New Request
