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PaulR
United Kingdom
9 Posts |
 Posted - 09 Sep 2009 : 09:48:33
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I'm working on several designs where the PCB layouts are very compact. When I run DRC check, I get many Pad-Silk and Pad-Via errors, even though (I judge) the text is sufficiently spaced from the pad or via.
It's not straightforward to work out how big E-PC thinks text is. The best way I've found is to put some text on a copper layer and pour copper around it. Doing this test with various text formats shows that the "size" of text is a rectangular zone around the text, but there's considerable space between (eg) the tops of the characters and the top of the zone. Further, this extra space gets bigger with larger text sizes. This means that larger text has to be spaced quite a long way from pads - much further than the setting of minimum text to pad/via clearance.
I can imagine it would be quite hard to work out clearances for truetype fonts on a curve-by-curve basis, but maybe it would be possible with the system stroke font?
It would also help if the "show clearances" function (display/setting&highlights) worked for text on silk layers relative to pads, when text is being positioned.
Ta, Paul
PaulR
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Clearances for Text on Silk layers
