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Mids01
United Kingdom
4 Posts |
 Posted - 12 Sep 2024 : 16:08:30
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Hi, I'm an occasional user of EasyPC and currently have an issue with a mod I'm making to a PCB layout.
I've implemented a minor mod to the schematic, 2 additional components, which has necessitated some tracking changes on the layout which I've done but I have an issue with a via shorting to a copper pour and some other tracks.
I can likely fix this issue fairly easily but my major concern is that this has not been picked by any of the checks carried out, i.e. Integrity check, connectivity check, etc.
Any advice as to why something so serious as this has not been flagged up?
I notice that the net in question contains exclamation marks within its name, is this some indication of an error? I can't find any reference to this in the user manual.
Many thanks.
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Edited by - Mids01 on 12 Sep 2024 16:09:06 |
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Iain Wilkie
United Kingdom
1019 Posts |
Posted - 12 Sep 2024 : 16:37:29
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Have you forward design changes ?
Did you do am un-pour/repour once you completed your mods ?
Have you run the design rule checker with the relevant checks enabled ?
Have you checked that the nets in question are correct in the schematic ? ..... Check to see if they are shorted (i.e. same net names)
Iain
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Mids01
United Kingdom
4 Posts |
Posted - 12 Sep 2024 : 16:45:17
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Yes, the changes have been forwarded. New components are positioned on the layout and tracked in. The unpour/repour should fix the issue to the pour area (not what happened with that previously).
The nets in question have different names.
As far as I'm aware I've run the design rule checker with the correct checks. I'm assuming I'm missing something here but it seems way too easy to miss such a fundamental problem. I would've thought it would be flagged up very obviously. |
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edrees
United Kingdom
781 Posts |
Posted - 12 Sep 2024 : 17:01:05
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| As per Iain, -but also perform a Design Integrity check. No way should this occur with all checks performed. |
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Mids01
United Kingdom
4 Posts |
Posted - 13 Sep 2024 : 13:47:09
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| Appreciate the feedback and suggestions but I'd really like to work out which check should find an issue such as this. Can it be narrowed down to a specific check of those listed? |
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edrees
United Kingdom
781 Posts |
Posted - 13 Sep 2024 : 14:06:25
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Start with a Schematic Design Rule check (For Whole Project), - with every check box ticked.
Then, if all OK, perform a "Forward Design Changes" and allow any changes to be made.
In PCB Editor, perform an Integrity check and correct any issues reported.
Then perform a PCB Design Rule check, -again, with every box ticked and "Whole Design" checked. You will probably find lots of errors, most can be ignored after some thought.
But if your "Spacings" and "Rules" in (PCB) Design Technology are incorrect, all the above may be in vain. (It allows 0 gap Track-Track and 0 gap Track to Pad spacing for example).
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Edited by - edrees on 13 Sep 2024 14:07:14 |
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Mids01
United Kingdom
4 Posts |
Posted - 13 Sep 2024 : 15:15:23
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I've now found the issue in relation to the various tests, Spacing in relation to Tracks, Pads, Shapes was not fully selected under the Tools/Design Rule Check. Ensuring the correct combination of those is selected highlights the error with the via in relation to the rest.
Next question, I select a copper pour area to Clear it and perform the Clear. What do I then select to perform the Pour again, there is no boundary apparent for the now cleared pour area?? |
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edrees
United Kingdom
781 Posts |
Posted - 13 Sep 2024 : 15:25:39
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quote:
there is no boundary apparent for the now cleared pour area??
Clearing the copper pour should leave the pour boundary definition in place, -if it hadn't already been already deleted leaving just the pour area in place. In this case you will have to re-draw the pour area.
But firstly make sure that "Pour Areas" is enabled/Displayed in (rainbow icon) Colours=> Layers and Layer Spans. |
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