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T O P I C R E V I E W
scottdoctor
Posted - 08 Aug 2024 : 19:39:44 I have version 27.0.1. My board is 4 layers. When I run the design rule checks on the PCB layout, I get an SoT fault wherever a track on the bottom layer goes under a surface mount pad that is on the top layer. I cannot find any settings or any other reason for the fault. The full text of the fault in the report is Solder Mask to Track : Required 5 actual 0. This happens for every track on the bottom side that goes under a surface mount pad on the top side.
Scott Doctor
1 L A T E S T R E P L I E S (Newest First)
edrees
Posted - 09 Aug 2024 : 09:04:08 1) Upgrade to 27.0.2
2)Are you sure that the pads of the Top layer components are NOT "All Layer" pads (without drill hole), or maybe a corrupt Design Tech file? Right click pad and then left click Properties from the drop down menu will tell you the pad information.
3) Are you sure that the "Layer Stack" is correct?