| T O P I C R E V I E W |
| greansleve |
Posted - 25 Feb 2015 : 10:51:38
Hi,
I'm in a situation where I have a schematic and a layout that both work and are correct, but they are 'out-of-sync' because somehow the net names on the layout have been changed. This means that now when I do the integrity check or DRC all the tracks on the layout are ripped up because they don't match the net names on the schematic, even though the connections were correct.
I want to 'resynchronize' the existing layout with the schematic without having to route all the ripped-up tracks in the same way they were on the existing layout.
What is the proper way to fix this?
At the moment I'm copying and pasting the tracks from the existing layout and auto-welding them in the new one.
Thanks. |
| 2 L A T E S T R E P L I E S (Newest First) |
| greansleve |
Posted - 27 Feb 2015 : 10:44:33
Thanks for your help John.
I figured out that the problem was caused by changing filenames which caused the sheetnames to mismatch. Can't really understand what happened but I started again, did one thing at a time and it worked.
Problem solved. |
| John Baraclough |
Posted - 26 Feb 2015 : 23:23:47
It sounds as though the nets in the PCB have been renamed. Back-annotation to the schematic should fix it. Make sure you keep a copy of both PCB layout and schematic in case something goes wrong.
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